<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 17 – Address Translation, TLB, and PTE > 17.9 IBox Instruction Translation

IBox performs instruction address translation independently of MBox data translation. During the Fetch (IF) stage, IBox translates the current PC through the ITB (Instruction Translation Buffer) to obtain the physical address for instruction fetch.

 

The ITB lookup uses the same SPAMShardManager infrastructure as the DTB, but with Realm::I (instruction) rather than Realm::D (data). ITB misses are handled differently from DTB misses: an ITB miss raises a translation fault that enters PAL mode, where the PAL miss handler walks the page table, inserts the result into the ITB, and retries the fetch.

 

ITB invalidation (onITB_IAWrite, onITB_ISWrite) additionally calls flushIPrefetchQueue() to discard any instructions fetched using the now-invalidated translation. This ensures that stale instruction translations do not survive in the fetch pipeline.

 

See Also: 14.1 IBox – Instruction Box; 3.4 Fetch Stage (IF).