<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 3 - Pipeline Architecture > 3.4 Fetch Stage (IF)

Responsibilities

 

The Fetch stage is the pipeline entry point. It is responsible for:

•Consuming the pending FetchResult supplied by IBox (via supplyFetchResult)

•Populating the PipelineSlot with the DecodedInstruction and resolved grain pointer

•Applying branch prediction — unconditional branches (BR/BSR) are always predicted taken with the target computed from the 21-bit displacement; conditional branches use a default predict-not-taken policy

•Advancing the PC via m_iprGlobalMaster->h->advancePC(nextPC)

•Assigning the slot sequence number (m_nextSequence++) for ordering and debugging

•Applying frontend stall conditions — if no valid FetchResult is pending, the stage produces an empty slot

 

What Fetch Does Not Do

 

•Commit PC updates — PC is architecturally committed only in WB

•Execute instructions — all execution occurs in EX

•Resolve branch conditions — condition evaluation occurs in EX, prediction update in WB

 

Branch Prediction in IF

 

Prediction metadata is stored in the slot for later resolution:

 

slot.predictionValid = true;

slot.predictionTaken = true; // unconditional: always taken

slot.predictionTarget = target; // computed from disp21

 

For unconditional branches, the target is calculated as (PC + 4) + (disp21 << 2). For conditional branches, the default prediction is not-taken with the fall-through address (PC + 4) as the predicted target.

 

See Also: 3.13 Flushing and Speculation; 4.4 IBox - Instruction Box (fetch frontend); CBoxLib/BranchPredictor.h.