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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 3 - Pipeline Architecture > 3.3 The Six Pipeline Stages |
The pipeline consists of six fixed stages. Stages execute from oldest to youngest (WB → MEM → EX → IS → DE → IF) within each cycle.
[0] Fetch (IF) — Instruction fetch, grain resolution, branch prediction, PC advancement
[1] Decode (DE) — Grain validation, execution Box routing, privilege checks
[2] Issue (IS) — Operand readiness, hazard checks, stall enforcement
[3] Execute (EX) — All architectural work: ALU, FP, memory, barriers, PAL
[4] Memory (MEM) — Deferred register commit (forwarding path), stall propagation
[5] Writeback (WB) — Architectural commit: store commit, fault dispatch, retirement
Invariant: No architectural state becomes visible until an instruction reaches WB. Any instruction that has not reached WB may be discarded without side effects.
See Also: Sections 3.4–3.9 for individual stage detail.