ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 3 - Pipeline Architecture

EMulatR implements a six-stage, in-order Alpha AXP pipeline optimized for clarity, correctness, and determinism. The pipeline is a single-issue, cycle-driven execution conveyor that models Alpha AXP execution behavior with weak ordering and precise exceptions.

Key characteristics:

•In-order issue and retirement — one instruction may retire per cycle

•All instruction semantics execute in a single stage (EX) via grain->execute(slot)

•Lightweight stages for bookkeeping and control flow

•Explicit stall and serialization handling with well-defined release conditions

•Precise exception semantics — no architectural state becomes visible until WB

•Backward stage advancement (WB → IF) for hazard-free forwarding

The pipeline is designed to model architectural behavior, not the microarchitectural speculation strategies of specific Alpha implementations. Its simplicity is intentional and enables correctness, debuggability, and long-term maintainability.

Pipeline state is owned exclusively by AlphaCPU. The pipeline is implemented as a ring buffer of six PipelineSlot entries, indexed by a rotating head pointer (m_head). Stage access is via the stage(N) accessor, which maps logical stage numbers to physical ring buffer positions.

static constexpr int STAGE_COUNT = 6; // IF, DE, IS, EX, MEM, WB

static constexpr int STAGEWB = 5;

static constexpr int STAGEMEM = 4;

static constexpr int STAGEEX = 3;

static constexpr int STAGEIS = 2;

static constexpr int STAGEDE = 1;

static constexpr int STAGEIF = 0;

See Also: 3.3 The Six Pipeline Stages; machineLib/PipeLineSlot.h; cpuCoreLib/AlphaPipeline.h.

3.2 Overview of the Pipeline Model

3.2 Overview of the Pipeline Model