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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 17 – Address Translation, TLB, and PTE > 17.8 TLB Invalidation and Shootdown |
Local TLB invalidation operates on a single CPU's SPAM shard. These operations are triggered by IPR writes from PAL code:
Operation |
Scope |
|---|---|
TBIA |
Invalidate all TLB entries (ITB + DTB), all ASNs, local CPU |
TBIAP |
Invalidate by ASN (ITB + DTB), local CPU — global (ASM) entries preserved |
TBIS |
Invalidate single VA (ITB + DTB), local CPU |
TBISI |
Invalidate single VA, ITB only, local CPU |
TBISD |
Invalidate single VA, DTB only, local CPU |
DTB_IA (IPR write) |
Invalidate all DTB entries, selecting DTB0 or DTB1 bank |
These operations map directly to SPAMShardManager methods: tbia(cpuId), invalidateASN(cpuId, asn), tbis(cpuId, va, asn). The IPR dispatch layer (onDTB_IAWrite, onITB_IAWrite, etc.) calls the appropriate globalEv6PteCache() invalidation method and, for ITB operations, also calls flushIPrefetchQueue() to discard any fetched instructions with stale translations.
When one CPU modifies page tables, other CPUs must invalidate their TLB entries for the affected mappings. This is accomplished via TLB shootdown — an explicit, synchronized IPI-based protocol:
CPU 0: Modifies page table entry in GuestMemory
CPU 0: Performs local TBIS/TBIA on own TLB
CPU 0: Broadcasts shootdown IPI to all other CPUs
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Target CPUs: Receive IPI via checkInterrupts()
Target CPUs: Enter PAL mode
Target CPUs: Call handleTLBShootdownIPI(cpuId, ipiData)
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Decode IPICommand:
TLB_INVALIDATE_ALL (0x01) → tbia(cpuId)
TLB_INVALIDATE_ASN (0x02) → invalidateASN(cpuId, asn)
TLB_INVALIDATE_VA_BOTH (0x03) → tbis(cpuId, va, asn)
TLB_INVALIDATE_VA_ITB (0x04) → ITB-only invalidate
TLB_INVALIDATE_VA_DTB (0x05) → DTB-only invalidate
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Target CPUs: Acknowledge IPI
CPU 0: Resumes after all targets acknowledge
Shootdowns are serialized operations — the initiating CPU stalls until all targets have acknowledged. This ensures that no CPU can execute with a stale TLB entry after the page table modification is complete.
The Tru64/EV6 guarantee specifies that any translation invalidation kills LL/SC reservations. TLB invalidation operations triggered by IPR writes, PAL code calls, context switches, and inter-processor invalidation must call ReservationManager::instance().clearAllReservations() as a side effect. This ensures that no STx_C can succeed against a mapping that has been invalidated — the physical address backing the reservation may no longer be correct.
Invariant: Shootdown is always explicit and synchronized — never implicit. No CPU may observe a page table modification without receiving and processing the corresponding shootdown IPI. Only coordination points are ASN epochs and explicit shootdowns.
See Also: 9.8 TLB Shootdown ; 9.6 Inter-Processor Interrupts (IPIs) ; 15.8 LL/SC Reservation Tracking; cpuCoreLib/AlphaCPU.h – handleTLBShootdownIPI().