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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 15 – Memory System Implementation Details > 15.8 LL/SC Reservation Tracking |
Reservations are tracked by the ReservationManager in cpuCoreLib/, not by GuestMemory or SafeMemory. Each CPU maintains exactly one active reservation at cache-line granularity (64 bytes, aligned via CACHE_LINE_MASK = ~63). The manager is constructed with the active CPU count and uses a fixed-size std::array<CPUReservation, MAX_CPUS> but only iterates over active entries.
The CPUReservation structure contains two fields: reservedCacheLine (the 64-byte-aligned physical address) and hasReservation (boolean).
Method |
Caller |
Behavior |
|---|---|---|
setReservation(cpuId, pa) |
LDL_L / LDQ_L |
Establish reservation on cache line containing PA |
checkAndClearReservation(cpuId, pa) |
STL_C / STQ_C |
Check if reservation matches; always clears; returns success/fail |
breakReservation(cpuId) |
Context switch, PAL |
Clear reservation for one CPU |
breakReservationsOnCacheLine(pa) |
Store commit |
Clear all CPU reservations matching this cache line |
Reservations are invalidated when any CPU writes to the same cache line (via breakReservationsOnCacheLine during write buffer drain), when the owning CPU executes STx_C (always clears regardless of success), when a barrier drains stores, when an exception or interrupt is taken, or when context switch or PAL entry occurs.
Invariant: LL/SC is optimistic — never blocking. A reservation can only succeed or fail; it never stalls.
See Also: cpuCoreLib/ReservationManager.h (~153 lines) – Complete reservation tracking class; 14.4 MBox – Memory Box (atomic operations).