<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 15 – Memory System Implementation Details > 15.9 Memory Barrier Coordination

15.9.1 Barrier Mechanics

 

Memory barriers do not perform memory I/O. Instead, they stall the pipeline, prevent fetch and speculation, wait until memory system conditions are satisfied (write buffer drain, read queue emptiness), and then release execution. Barrier correctness depends entirely on write buffer state and SMP coordination.

 

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15.9.2 MemoryBarrierCoordinator – SMP Global Barriers

 

The MemoryBarrierCoordinator is a singleton that coordinates cross-CPU memory barrier acknowledgment. When a CPU executes an MB instruction in an SMP system with more than one active CPU, the CBox calls initiateGlobalMemoryBarrier(cpuId, activeCpuCount). This sets the barrierInProgress flag, initializes the participant count, and the initiating CPU immediately acknowledges. Other CPUs acknowledge via acknowledgeMemoryBarrier(cpuId), which calls Alpha::Memory::fullBarrier() (a host-side memory fence) before incrementing the atomic acknowledged counter.

 

The initiating CPU blocks in waitForBarrierAcknowledge() on a QWaitCondition until all participating CPUs have acknowledged. A 2-second timeout triggers a machine check exception (SMP barrier timeout) if the MCES<MME> IPR bit is enabled. When all CPUs have acknowledged, completeGlobalMemoryBarrier() clears the barrier state and wakes all waiters.

 

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15.9.3 Source Files

 

 

See Also: Chapter 6 - Serialization and Stall Model; 14.5.4 CBox – Cache / Control Box (serialization types); grainFactoryLib/MemoryBarrier_core.h – Barrier type definitions.