<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 15 – Memory System Implementation Details > 15.10 SMP Visibility Guarantees

In SMP systems, each CPU has independent write buffers managed by the WriteBufferManager. Barriers coordinate global visibility through the MemoryBarrierCoordinator. The CBox orchestrates cross-CPU ordering by initiating barrier sequences that require all active CPUs to acknowledge before releasing the initiating CPU's pipeline.

 

No CPU may observe reordered writes past a completed barrier. No CPU may observe stale values after a barrier completes and all write buffers have drained. IPIs may be used for global synchronization to notify remote CPUs of pending barriers.

 

The barrier coordinator tracks per-barrier state: participatingCpus (total count), acknowledgedCpus (atomic counter), initiatingCpu (the CPU that started the barrier), and barrierInProgress (global flag). A barrier completes when acknowledgedCpus == participatingCpus.

 

See Also: 11.3 Memory Model Invariants; coreLib/IPI_core.h – Inter-processor interrupt definitions.