<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 11 - Architectural Invariants > 11.3 Memory Model Invariants

11.3.1 Weak Ordering by Default

 

Memory is weakly ordered. Loads and stores may reorder. Stores may be deferred (via per-CPU write buffers). Visibility is not guaranteed without barriers. No implicit ordering exists.

 

Enforced by: WriteBufferManager defers stores per-CPU, GuestMemory provides no cross-CPU ordering guarantees, loads may observe stale values from local caches.

 

---

 

11.3.2 Explicit Ordering Only

 

Ordering is enforced only by: MB/WMB (memory barriers), EXCB/TRAPB (exception/trap barriers), PAL entry/exit (implicit full serialization), and certain MMIO semantics (strong ordering). Any code relying on implicit ordering is incorrect.

 

Enforced by: CBox barrier implementations (executeMB/WMB/TRAPB/EXCB), MemoryBarrierCoordinator for global coordination, pipeline stall/release mechanics in stage_MEM().

 

---

 

11.3.3 MMIO Strong Ordering

 

MMIO accesses are strongly ordered, synchronous, never buffered, and never speculative. MMIO correctness overrides performance.

 

Enforced by: MMIO writes bypass WriteBufferManager, MMIOManager dispatches synchronously in EX stage, MMIOWindow::stronglyOrdered flag, pipeline stalls until MMIO access completes.

 

See Also: Chapter 5 - Memory System Architecture; Chapter 6 - Serialization and Stall Model; Chapter 10 – Devices and Memory-Mapped I/O (MMIO).