ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 11 - Architectural Invariants > 11.4 Load-Locked / Store-Conditional Invariants

11.4.1 Reservation Model

LL/SC uses reservations, not locks. Reservations are per-CPU, cache-line granular (64 bytes), optimistic, and non-blocking. No mutex semantics exist.

Enforced by: ReservationManager with one CPUReservation slot per CPU, cache-line-aligned physical address matching.

11.4.2 Reservation Lifetime

A CPU may hold at most one reservation. Reservations are cleared on: any store to the same cache line (local or remote, via breakReservationsOnCacheLine()), MB/EXCB where required, PAL entry or exit, exception or interrupt delivery, and context switch. Reservations never survive privilege boundaries.

Enforced by: ReservationManager::breakReservation(cpuId) called from enterPal(), executeREI(), FaultDispatcher delivery path. breakReservationsOnCacheLine() scans all CPUs on every store commit in WB.

11.4.3 Store-Conditional Semantics

ST*_C must: succeed only if reservation is valid, fail otherwise, and clear the reservation regardless of outcome. No retries are implicit.

Enforced by: MBox::executeSTL_C()/STQ_C() check ReservationManager::checkReservation(cpuId, pa), write R_a = 1 (success) or R_a = 0 (failure), always call clearReservation(cpuId).