ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 11 - Architectural Invariants

11.2.1 Precise Execution

All exceptions are precise. When an exception is delivered: all prior instructions have completed, no later instruction has modified architectural state, and no instruction partially commits. There are no imprecise exceptions in EMulatR.

Enforced by: detect-early/deliver-late model — faults detected in EX stage (slot.faultPending), not delivered until WB stage. Younger pipeline slots invalidated on delivery. FaultDispatcher queues events and controls delivery timing.

11.2.2 Single Commit Point

Architectural state commits only in Writeback (WB). No instruction updates architectural state earlier. Speculative results are never visible. This applies to registers, PC, condition codes, and memory visibility.

Enforced by: pipeline stages IF→EX→MEM→WB with EX producing results into slot temporaries, WB writing to architectural register files.

11.2.3 EX Stage Authority

All instruction semantics execute in EX stage. Memory operations occur in EX via MBox. Other pipeline stages perform bookkeeping only. No architectural work occurs outside EX.

Enforced by: grain→execute() called in EX stage, returning BoxResult. All execution box dispatch (EBox, FBox, MBox, CBox, PalBox) occurs within EX.

11.2.4 No Speculation Across Serialization Points

No speculative instruction may execute past: MB, WMB, EXCB, TRAPB, CALL_PAL, or HW_REI. Serialization points are absolute.

Enforced by: slot.stalled flag in stage_MEM() stall check, slot.needsMemoryBarrier/needsWriteBufferDrain flags, pipeline flush on CALL_PAL and HW_REI (BoxResult::flushPipeline()), frontend fetch blocked while any slot is stalled.

11.2 Execution and Pipeline Invariants

11.2 Execution and Pipeline Invariants

11.2.1 Precise Execution

11.2.2 Single Commit Point

11.2.3 EX Stage Authority

11.2.4 No Speculation Across Serialization Points