<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 14 – Execution Domains (“Boxes”) > 14.5 CBox – Cache / Control Box

The CBox manages the cache subsystem, write buffering, memory barriers, branch prediction, and control-flow transfer instructions. On the 21264, the Cbox controlled the L2 cache, the system bus interface, probe handling, and write buffer draining. In EmulatR, the CBox serves as the pipeline's control-flow and memory-ordering authority, coordinating write buffer commits to GuestMemory, enforcing MB/WMB/TRAPB/EXCB serialization semantics, and housing the branch predictor.

 

14.5.1 Responsibilities

 

•Write buffer management: queueing, draining, and committing deferred stores to GuestMemory

•Memory barriers: MB (full barrier), WMB (write barrier), TRAPB (trap barrier), EXCB (exception barrier)

•Branch prediction: 2-bit saturating counter BHT (BranchPredictor), prediction, update, flush

•Control-flow instructions: BR, BSR, BEQ, BNE, BLT, BLE, BGT, BGE, BLBC, BLBS, FBEQ, FBNE, FBLT, FBLE, FBGT, FBGE

•Jump instructions: JMP, JSR, RET, JSR_COROUTINE (via Rb-based indirect target)

•Cache maintenance: ECB (evict cache block), FETCH, FETCH_M

•Cycle counter: RPCC (read process cycle counter)

•HALT execution and halt-callback notification

•MMIO completion tracking

•IPR management: Process Context Block Base (PCBB) pointer updates, staged IPR write commits

 

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14.5.2 CBox State Machine

 

The CBox operates in one of three states, defined by the CBoxState enumeration:

 

 

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14.5.3 Branch Prediction

 

The CBox contains an instance of BranchPredictor, which implements a 2-way set-associative branch history table using 2-bit saturating counters (strongly not-taken / weakly not-taken / weakly taken / strongly taken). The predictor supports three strategies selectable via the ICCSR register: NeverTaken (always predict fall-through), DisplacementBased (predict taken for negative displacement, not-taken for positive), and HistoryTable (full 2-bit counter prediction). On each branch resolution, the CBox calls updatePrediction() to train the counter.

 

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14.5.4 Serialization Types

 

The cBox_core.h file defines the SerializationType enumeration used to classify barrier semantics:

 

enum class SerializationType {

    Barrier_MB,     // MB  – Full memory barrier

    Barrier_TRAP,   // TRAPB – Trap barrier

    Barrier_WRITE,  // WMB – Write memory barrier

    Barrier_EXC,    // EXCB – Exception barrier

    Barrier_NONE    // No serialization

};

 

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14.5.5 Source Files

 

 

See Also: memoryLib/WriteBufferManager.h – Write buffer queueing and drain logic; memoryLib/global_MemoryBarrierCoordinator.h – Cross-CPU barrier coordination; coreLib/WriteBufferEntry.h – Individual write buffer entry structure; mmioLib/global_mmioManager.h – MMIO dispatch and completion.