<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 14 – Execution Domains (“Boxes”) > 14.6 PalBox – Privileged Architecture Library Execution Box

The PalBox is an EmulatR-specific execution domain that has no direct hardware counterpart on the 21264 die. On real Alpha silicon, PALcode executed as privileged Alpha instructions with access to hardware-internal processor registers (IPRs) through HW_MFPR and HW_MTPR opcodes. In EmulatR, the PalBox encapsulates all PAL mode entry/exit logic, CALL_PAL dispatch, IPR access, shadow register management, and system service routing. It delegates the actual PAL service implementations to PalService (palLib_EV6/).

 

14.6.1 Responsibilities

 

•CALL_PAL dispatch: decode the 8-bit function code from instruction bits [7:0] and route to the appropriate PAL service handler

•Privileged PAL calls: HALT, CFLUSH, DRAINA, CSERVE, IMB, INITPAL, and various DTB/ITB management

•Unprivileged PAL calls: BPT, BUGCHK, CALLSYS, GENTRAP, KBPT, and the CHMx (Change Mode) family – CHME, CHMK, CHMS, CHMU

•Queue manipulation: INSQHIL, INSQHILR, INSQHIQ, INSQHIQR, INSQTIL, INSQTILR, INSQTIQ, INSQTIQR, INSQUEL, INSQUEQ

•HW_MFPR / HW_MTPR: read and write internal processor registers (ASN, ASTEN, ASTSR, ESP, FEN, IPL, SSP, USP, etc.)

•PAL mode entry (enterPal): save context, activate shadow registers, compute entry PC from PalVectorTable, set PAL mode flag

•PAL mode exit (RTI – Return from Interrupt): restore context, deactivate shadow registers, return to interrupted PC

•Exception handling: route machine checks, arithmetic traps, memory faults, and alignment faults to the appropriate PAL vector

•Shadow register management: activate/deactivate the PAL shadow register bank for R0–R7 during PAL mode transitions

 

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14.6.2 PAL Entry Flow

 

When a CALL_PAL instruction is decoded by the IBox or an exception is raised by any box, the PalBox's enterPal() method is invoked with a PalEntryReason, a vector or selector, and the faulting PC. The method saves the current context (PC, processor status), activates PAL shadow registers, looks up the entry point from the PalVectorTable, and transfers control. The actual PAL service logic then executes within PalService, which may perform HW_MFPR/HW_MTPR operations, queue manipulations, or TLB management before returning a BoxResult that indicates how execution should resume.

 

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14.6.3 Source Files

 

 

See Also: palLib_EV6/PalVectorTable_final.h – PAL vector table definitions; palLib_EV6/Pal_Service.h – PalService class (actual PAL operation implementations); palLib_EV6/Pal_core_inl.h – PAL core inline helpers; palLib_EV6/PAL_core.h – PAL constants and entry reason enumeration.