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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 14 – Execution Domains (“Boxes”) > 14.7 Box Interaction Model |
The six boxes do not call each other directly. Instead, they communicate through four shared mechanisms:
Mechanism |
Role in Box Communication |
|---|---|
PipelineSlot |
Primary data transport. Carries the DecodedInstruction, register read accessors, and payLoad result field through every box that touches the instruction. Each box reads inputs from and writes results to the slot. |
IPR State Views |
Every box holds a per-CPU pointer (m_iprGlobalMaster) to the shared IPR storage, providing read/write access to the architectural PC, processor status, FPCR, and hardware registers. This is the shared architectural state backbone. |
GuestMemory |
Shared physical memory subsystem. The IBox reads instructions, the MBox reads/writes data, and the CBox commits write-buffer entries through this interface. |
FaultDispatcher |
Per-CPU fault sink. Any box can post a fault (translation miss, arithmetic trap, alignment fault) which is then routed to the PalBox for PAL-mode exception handling. |
This decoupled design ensures that each box can be developed, tested, and debugged in isolation, and that the emulator's execution model remains deterministic and cycle-reproducible.
See Also: Chapter 13 – AlphaPipeline Implementation (PipelineSlot); Chapter 15 – Memory System Implementation Details (GuestMemory, WriteBufferManager); Chapter 17 – Address Translation, TLB, and PTE ; Chapter 18 – Fault Dispatcher & Precise Exceptions (FaultDispatcher).