ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 14 – Execution Domains (“Boxes”) > 14.4 MBox

The MBox executes all memory-referencing instructions: integer and floating-point loads and stores, unaligned accesses, locked load/store-conditional pairs for atomic operations, and cache-hint instructions. On the 21264, the Mbox owned the data cache (Dcache), the data-stream TLB (DTB), the miss-address file (MAF), and the address generation datapath. In EmulatR, the MBox integrates TLB translation (via the Ev6SiliconTLB singleton), physical memory access (via GuestMemory), and reservation tracking (via ReservationManager) for LDx_L/STx_C atomicity.

14.4.1 Responsibilities

•Integer loads: LDL, LDQ, LDQ_U, LDBU, LDWU

•Integer stores: STL, STQ, STQ_U, STB, STW

•Floating-point loads: LDF, LDG, LDS, LDT

•Floating-point stores: STF, STG, STS, STT

•Locked load / store-conditional: LDL_L, LDQ_L, STL_C, STQ_C (via ReservationManager)

•Address calculation (LDA, LDAH executed in MBox path)

•VA-to-PA translation with staged PTE cache for PAL IPR updates

•Cache-hint NOPs: ECB, WH64, WH64EN, FETCH, FETCH_M

•Miscellaneous: RPCC (read process cycle counter), RDUNIQUE/WRUNIQUE

•Bit-manipulation extensions (EV67 CIX): CTPOP, CTLZ, CTTZ

14.4.2 Address Translation Flow

For every memory operation, the MBox calculates the effective address (Rb + sign-extended displacement) and then translates the virtual address to a physical address via the EV6 TLB. The translation path supports two modes: normal TLB lookup through the Ev6SiliconTLB singleton, and staged PTE lookup through the StagedPTECache for PAL-mode IPR-driven TLB fill operations. The translateWithStagedEntry() method attempts the staged cache first (for active PAL TLB fill flows), then falls through to the hardware TLB.

14.4.3 Atomic Operations – LDx_L / STx_C

The LDL_L and LDQ_L instructions perform a load and establish a per-CPU reservation on the target physical address via the global ReservationManager. The subsequent STL_C or STQ_C checks the reservation: if the address is still reserved for this CPU, the store succeeds and Ra is set to 1; if the reservation has been cleared (by another CPU's store or a barrier), the store is suppressed and Ra is set to 0. This implements the Alpha's compare-and-swap primitive for lock-free algorithms.

14.4.4 Code Example – Load Quadword

AXP_HOT AXP_ALWAYS_INLINE void executeLDQ(PipelineSlot& slot) noexcept

{

// Calculate effective address: Rb + SEXT(displacement)

quint64 va = calculateEffectiveAddress(slot);

// Translate VA -> PA via TLB

ev6TranslationResult xlat;

if (!translateWithStagedEntry(va, xlat, slot))

return; // Translation fault — dispatched to FaultDispatcher

// Read 8 bytes from physical memory

quint64 data = 0;

m_guestMemory->read64(xlat.physAddr, data);

slot.payLoad = data;

}

14.4.5 Source Files

File	Lines (approx)	Content
MBoxLib_EV6/MBoxBase.h	~2,256	Complete MBox class: loads, stores, translation, LDx_L/STx_C, IPR staging
MBoxLib_EV6/MBoxBase.cpp	~24	Compilation unit include (breaks circular dependency)