<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 14 – Execution Domains (“Boxes”) > 14.3 FBox – Floating-Point Execution Box

The FBox handles all IEEE 754 floating-point arithmetic. On the 21264, the Fbox comprised two floating-point pipelines (add and multiply), a divide unit, a square root unit, and a 72-entry FP register file. In EmulatR, the FBox executes FP operations using host-native double-precision arithmetic modulated by the FPCR (Floating-Point Control Register) and FPVariant qualifiers that encode rounding mode, trapping behavior, and precision.

 

14.3.1 Responsibilities

 

•IEEE arithmetic: ADDS/ADDT, SUBS/SUBT, MULS/MULT, DIVS/DIVT, SQRTS/SQRTT (with all rounding/trapping suffix variants: /C, /M, /D, /U, /SU, /SUI, etc.)

•Comparison: CMPTEQ, CMPTLT, CMPTLE, CMPTUN

•Conversion: CVTTS, CVTST, CVTTQ, CVTQS, CVTQT, CVTLQ, CVTQL

•FP conditional move: FCMOVEQ, FCMOVNE, FCMOVLT, FCMOVGE, FCMOVLE, FCMOVGT

•Sign manipulation: CPYS, CPYSN, CPYSE

•FPCR management: MT_FPCR (Move To), MF_FPCR (Move From)

•Multi-cycle operation simulation with busy/cyclesRemaining tracking

•FP register scoreboard (m_fpRegisterDirty[32]) for hazard detection

 

---

 

14.3.2 FPVariant and FPCR Integration

 

Every FBox arithmetic method accepts an FPVariant parameter that encodes the instruction's rounding mode (/C chopped, /M minus-infinity, /D dynamic from FPCR), underflow behavior (/U), software-complete trapping (/S), and inexact reporting (/I). The FBox calls deriveLocalFpcr() to merge the per-instruction variant with the architectural FPCR value, producing a local FPCR that governs that specific operation. This design allows the same underlying arithmetic path to handle all 16 suffix combinations per base instruction.

 

---

 

14.3.3 Code Example – Floating-Point Add

 

AXP_HOT AXP_ALWAYS_INLINE void executeAdd(PipelineSlot& slot,

                                              const FPVariant& variant) noexcept

{

    auto* iprs = m_iprGlobalMaster;

    quint64 fpcrLocal = deriveLocalFpcr(iprs->fpcr, variant);

    const double srcA = slot.readFpRegAsDouble(slot.di.ra);

    const double srcB = slot.readFpRegAsDouble(slot.di.rb);

    const double result = addF64_variant(srcA, srcB, fpcrLocal, variant);

    slot.writeFpRegFromDouble(slot.di.rc, result);

}

 

---

 

14.3.4 Source Files

 

 

See Also: coreLib/fp_variant_core.h – FPVariant definition and encoding; coreLib/alpha_fp_helpers_inl.h – FP arithmetic primitives; coreLib/alpha_fp_ieee_inl.h – IEEE 754 compliance helpers; coreLib/alpha_fpcr_core.h – FPCR field definitions and deriveLocalFpcr().