ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 13 – AlphaPipeline Implementation

The AlphaPipeline is a single-issue, in-order, cycle-driven pipeline that models Alpha AXP execution with weak ordering and precise exceptions. Key principles: one instruction may retire per cycle, instructions advance one stage per cycle unless stalled, all execution happens in EX stage, commit occurs only in WB stage, pipeline state is owned exclusively by AlphaCPU.

Three critical design decisions documented in the header define the pipeline's correctness model:

1. Register writeback in MEM stage (not WB) — ALL register writes occur in stage_MEM() via commitPending(). stage_WB() only handles store commits, retirement, and exception dispatch. This resolves RAW hazards through intra-cycle ordering.

2. Memory store commits in WB stage — stores do NOT write to memory in stage_MEM(). Stores commit in stage_WB() after all hazards are cleared, ensuring stores can be rolled back on exceptions.

3. RAW hazard resolution without forwarding — no forwarding logic required, no pipeline stalls for register dependencies. Because stage_MEM() executes BEFORE stage_EX() in the same cycle (reverse execution order WB→MEM→EX→IS→DE→IF), the younger instruction in EX reads the value that the older instruction in MEM just wrote.

See Also: Section 3.3 – Pipeline Stages (conceptual); Section 11.2 – Execution Invariants.

13.2 Pipeline Role and Design

13.2 Pipeline Role and Design