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13.3.1 Stage Constants

 

static constexpr int STAGE_COUNT = 6;

static constexpr int STAGEIF = 0; // Instruction Fetch (youngest)

static constexpr int STAGEDE = 1; // Decode

static constexpr int STAGEIS = 2; // Issue

static constexpr int STAGEEX = 3; // Execute — ALL real work here

static constexpr int STAGEMEM = 4; // Memory — register writeback

static constexpr int STAGEWB = 5; // Writeback — store commit, retirement (oldest)

 

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13.3.2 Ring Buffer Implementation

 

The pipeline uses a 6-slot circular buffer:

 

QVarLengthArray<PipelineSlot, STAGE_COUNT> m_slots; // Physical slots [0..5]

int m_head = 0; // Index of oldest instruction (always WB)

 

The stage() accessor maps logical stage indices to physical ring buffer positions:

 

PipelineSlot& stage(int logicalIndex) noexcept {

 return m_slots[(m_head - logicalIndex + STAGE_COUNT) % STAGE_COUNT];

}

 

Mapping: stage(5/WB) = m_slots[m_head] (oldest), stage(4/MEM) = m_slots[(m_head-1+6)%6], stage(3/EX) = m_slots[(m_head-2+6)%6], stage(2/IS) = m_slots[(m_head-3+6)%6], stage(1/DE) = m_slots[(m_head-4+6)%6], stage(0/IF) = m_slots[(m_head-5+6)%6] (youngest).

 

advanceRing() rotates the buffer at the end of each tick: m_head = (m_head + 1) % STAGE_COUNT. This causes each instruction to "flow forward" one stage — IF→DE→IS→EX→MEM→WB.

 

See Also: cpuCoreLib/AlphaPipeline.h (ring buffer comments lines 60–190).