<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 13 – AlphaPipeline Implementation > 13.4 PipelineSlot Structure

Each stage holds a PipelineSlot (PipeLineSlot.h, 409 lines) representing one in-flight instruction. Key fields:

 

Instruction identity: di (DecodedInstruction — PC, raw bits, operand indices, semantics bitmask), grain (const InstructionGrain* — resolved execution function pointer), slotSequence (monotonic age counter for fault precedence).

 

Control state: valid (slot contains a live instruction), stalled (slot cannot advance), faultPending (exception detected, awaiting delivery), flushPipeline (grain requested pipeline flush).

 

Execution results: payLoad (quint64 — result value from EX), branchTaken (bool), branchTarget (quint64), nextPC (sequential or branch target), pcReason (Sequential, Branch, Jump, PAL, etc.).

 

Serialization: needsMemoryBarrier / memoryBarrierCompleted, needsWriteBufferDrain / writeBufferDrained — barrier completion flags checked in stage_MEM() stall logic.

 

Fault info: trapCode (TrapCode_Class), faultVA (faulting virtual address), faultPC (faulting instruction PC).

 

Deferred writeback: m_pending (PendingCommit) — holds deferred register writes. PendingCommit contains: intValid/fpValid flags, intReg/fpReg destination register indices, intValue/fpValue result values, intClearDirty/fpClearDirty for dirty-bit management, instrPC for tracing. Deferred writes are committed by commitPending() in stage_MEM() (one stage later than execution).

 

Slots are lightweight and reused aggressively — clear() resets all fields to defaults.

 

See Also: machineLib/PipeLineSlot.h.