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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 13 – AlphaPipeline Implementation > 13.5 Pipeline Execution - tick() and execute() |
tick() is called once per cycle by AlphaCPU::runOneInstruction(). It supplies the IBox fetch result to the pipeline, calls execute() to run all six stages, rotates the ring buffer, increments the cycle counter, and returns a BoxResult indicating pipeline state.
execute() runs all six stages in reverse order (oldest to youngest):
BoxResult execute(FetchResult& fetchResult) {
stage_WB(result); // Stage 5: retire, commit stores
// → early return if FAULT or PAL_CALL detected
stage_MEM(); // Stage 4: register writeback via commitPending()
// → check for EX-stage flush request, fault detection
stage_EX(); // Stage 3: grain→execute(), branch resolution
// → check for EX-stage flush request, fault detection
stage_IS(); // Stage 2: issue (mostly pass-through)
stage_DE(); // Stage 1: decode (mostly pass-through)
stage_IF(); // Stage 0: consume pending fetch
// → check stalls, branch misprediction
return BoxResult().advance();
}
The reverse order (WB→MEM→EX→IS→DE→IF) is the critical correctness mechanism: stage_MEM writes registers before stage_EX reads them in the same cycle, eliminating the need for forwarding logic. After WB, faults are checked and may cause early return with BoxResult::faultDispatched(). After EX, flush requests (slot.flushPipeline) are checked and younger stages are invalidated.
See Also: Section 12.5 – runOneInstruction() (calls tick()).