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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 8 - PAL and Privileged Boundary > 8.13 Summary |
The EMulatR PAL implementation provides a precise, verifiable privileged boundary that mirrors Alpha AXP hardware behavior.
1.PAL is a hardware-defined privileged execution mode — not microcode, not firmware, part of the architectural contract
2.Privilege is binary: PAL or non-PAL — no intermediate states, no partial privilege
3.CALL_PAL is the only entry — serializes pipeline, drains buffers, clears reservations, flushes pipeline, sets PC|0x1/IPL=7/CM=KERNEL
4.HW_REI is the only exit — full register-context restore via restoreContext(), pipeline flush, serialization
5.PAL vectors are architecture-defined — 12 EV6 exception vectors (0x0000–0x0580) plus 128 CALL_PAL dispatch entries (privileged at 0x2000+, unprivileged at 0x3000+)
6.PalEntryReason classifies entry (10 values) — determines vector computation and context save behavior
7.PAL entry implies full serialization — stronger than MB + EXCB combined
8.LL/SC reservations cannot span PAL boundaries — cleared on both entry and exit
9.Enforcement is multi-layered — instruction-level (OPCDEC faults), pipeline-level (serialization/flush), memory-level (buffer drain, reservation clear), exception-level (precise delivery)
10.PAL is implemented as C++ code — PalBoxBase delegates to PalService, no PAL code in memory, eliminates memory synchronization issues
See Also: Chapter 9 - SMP Architecture( next chapter).