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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 13 – AlphaPipeline Implementation > 13.8 Flush Semantics |
Pipeline flush occurs on: branch misprediction (slot.flushPipeline from EX), exception delivery (from runOneInstruction after BoxResult), interrupt delivery (handleInterrupt()), CALL_PAL (from stage_WB PAL_CALL path), HW_REI (executeREI()), and fatal fault.
The flush() implementation:
void flush(const char* caller) {
stage(m_head).m_pending = PendingCommit{}; // Clear pending commit
for (int i = 0; i < STAGE_COUNT; i++) {
stage(i).clear();
stage(i).valid = false;
}
if (m_mBox) {
m_mBox->clearMissStaging();
m_mBox->clearIPRStaging();
}
}
All slots are invalidated, pending commits are discarded, and MBox staging state is cleared. The clearMissStaging() call discards any in-progress TLB fill that has not yet been committed to the TLB — without this, a speculative TLB fill from a flushed instruction could corrupt the translation buffer. The clearIPRStaging() call discards any staged IPR write that has not yet been committed — without this, a flushed HW_MTPR could silently modify privileged state.
Flush is logged via EXECTRACE_PIPELINE_FLUSH with the caller name and current PC. The caller parameter identifies the flush source for debugging (e.g., "stage_WB:FAULT", "handleInterrupt", "executeREI"). After flush, fetch restarts at the corrected PC. Flushes are precise and deterministic — identical inputs always produce identical flush behavior.
Partial flush (flushYoungerSlots()) occurs when EX sets slot.flushPipeline — execute() invalidates stages 0 through STAGEEX−1 (IF, DE, IS) while preserving EX, MEM, and WB. This is the branch misprediction path: the mispredicted instruction in EX has already produced its result, and older instructions in MEM and WB must still retire. Only the younger speculatively-fetched instructions are discarded.
After partial flush, IBox refetches from the corrected branch target on the next cycle. The EX slot advances normally through MEM and WB.
See Also: Section 3.15 – Flush Mechanics; Chapter 22 – Testing, Validation, and Architectural Compliance (flushYoungerSlots verification).