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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 13 – AlphaPipeline Implementation > 13.9 Serialization and Barriers in Pipeline |
Barrier instructions (MB, WMB, EXCB, TRAPB) do not execute computational work — they enforce ordering. In stage_EX(), the grain sets the appropriate stall flag. In stage_MEM(), the flag is checked: if the barrier has not completed, the slot stalls.
MB (Memory Barrier) — sets slot.needsMemoryBarrier = true. Requires global visibility: all prior stores must be visible to all CPUs. CBox coordinates with MemoryBarrierCoordinator, which in SMP configurations ensures all CPUs acknowledge the barrier. This is the most expensive barrier — it may stall for multiple cycles while cross-CPU coordination completes.
WMB (Write Memory Barrier) — sets slot.needsWriteBufferDrain = true. Requires local write ordering only: all prior stores must drain from the local write buffer. No cross-CPU coordination is needed. CBox sets writeBufferDrained = true when the local write buffer is empty.
EXCB (Exception Barrier) — sets slot.needsMemoryBarrier = true. Requires all prior instructions to complete and all pending exceptions to be resolved before any younger instruction issues. Uses the same stall mechanism as MB but the completion condition is exception resolution rather than store visibility.
TRAPB (Trap Barrier) — sets slot.needsMemoryBarrier = true. Requires all prior instructions that may generate arithmetic traps to have completed. Specifically targets floating-point trap completion. Uses the same stall path as EXCB.
CBox is responsible for completing all barriers. The pipeline never self-clears a barrier flag. The completion path: CBox evaluates the barrier condition on each tick, and when satisfied, sets the completion flag (memoryBarrierCompleted or writeBufferDrained) on the stalled slot. On the next tick, stage_MEM() finds the flag set, performs commitPending() normally, and the slot advances to WB.
CALL_PAL is the strongest serialization point. It is detected in stage_WB() and triggers PipelineAction::PAL_CALL, which causes AlphaCPU to flush the entire pipeline, drain all write buffers, clear LL/SC reservations, and enter PAL mode. No instruction survives a CALL_PAL boundary in either direction.
HW_REI is the corresponding exit serialization point. It flushes the pipeline, restores context from EXC_ADDR, clears PAL mode (PC bit 0), and clears LL/SC reservations. No speculative instruction from PAL mode survives into normal execution.
Together, CALL_PAL and HW_REI form a hard boundary: the pipeline is fully drained on entry and fully drained on exit. This is architecturally required — PAL mode operates with shadow registers and privileged state that must not leak across the boundary.
See Also: Chapter 6 - Serialization and Stall Model ; Chapter 15 – Memory System Implementation Details (MemoryBarrierCoordinator); Chapter 20 – Boot Sequence, PAL, and SRM Integration (CALL_PAL/HW_REI serialization).