<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 20 – PAL Emulation & Boot Sequence

This chapter describes the implementation of the EMulatR Privileged Architecture Library (PAL) emulation layer and the boot sequence that brings the system from reset to the SRM console prompt. Where Chapter 8 defines the architectural contract — what PAL is, how privilege is enforced, entry/exit semantics — this chapter covers the concrete PalBox execution domain, PalService delegation model, CALL_PAL dispatch, shadow register management, HWPCB context handling, privileged instruction implementation, CSERVE console services, and the phased boot sequence.

 

A key design decision: EMulatR implements PAL as C++ code executed through PalService methods, not as Alpha instructions stored in memory. CALL_PAL instructions execute C++ handlers via PalBoxBase → PalService delegation. There is no PAL code stored in GuestMemory — this eliminates an entire class of memory synchronization issues while faithfully implementing the architectural interface.

 

Scope: This chapter covers PalBox responsibilities and architecture, PalService delegation, CALL_PAL dispatch and vector calculation, PAL mode entry and exit (enterPal/HW_REI), shadow registers, HWPCB context management, privileged instructions (HW_MFPR/HW_MTPR/HW_LD/HW_ST), CSERVE console services, the SRM boot sequence, and the PAL function inventory. It does not re-cover the architectural privilege model (Chapter 8), fault delivery mechanics (Chapter 18), or interrupt delivery (Chapter 19).

 

See Also: Chapter 8 - PAL and Privileged Boundary (architectural contract); 14.6 PalBox – Privileged Architecture Library Execution Box (box overview); Chapter 18 – Fault Dispatcher & Precise Exceptions (event delivery to PAL).