<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 3 - Pipeline Architecture > 3.6 Issue Stage (IS)

Responsibilities

 

The Issue stage performs hazard and readiness checks before an instruction enters the Execute stage:

•Source operand availability

•Register dependency checks (RAW, WAR, WAW hazards)

•Functional domain availability

•Scoreboarding and result forwarding

 

If requirements are not met, the slot is stalled in Issue. A stalled slot blocks all younger stages from advancing.

 

In-Order Discipline

 

Instructions issue in strict program order. No instruction bypasses an older stalled instruction. This preserves simple and predictable execution semantics and eliminates the need for complex reorder logic.

 

Implementation Note

 

In the current implementation, hazard checks have been migrated into the Boxes themselves. The Issue stage advances the slot's currentStage counter and checks the stalled flag. If the slot is stalled or invalid, the stage returns immediately and logs a diagnostic message. Future enhancements may include dual-issue logic at this stage.

 

See Also: 3.12 Stalls and Serialization; Chapter 13 – AlphaPipeline Implementation.