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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 12 – AlphaCPU Core > 12.7 Interrupt and Exception Handling |
AlphaCPU checks for interrupts at the start of every cycle (before fetch). The handleInterrupt() method:
void handleInterrupt() {
if (!m_pending->hasDeliverable(currentIPL)) return;
ClaimedInterrupt claimed = m_pending->claimNext(currentIPL);
if (!claimed.valid) return;
m_pBox->palService()->clearSisrIfSoftware(claimed);
m_reservationManager->breakReservation(m_cpuId);
m_pBox->palService()->deliverInterrupt(claimed);
m_alphaPipeline->flush("flush::interruptDelivery");
}
Key sequence: claim highest-priority deliverable interrupt, clear SISR bit if software interrupt, break LL/SC reservation, deliver through PalService (enters PAL), flush pipeline. Interrupts never interrupt instruction execution mid-cycle — they are checked before the next fetch.
Faults detected during execution return via BoxResult flags from the pipeline tick. AlphaCPU handles them in runOneInstruction() only when boxResult.faultWasDispatched() is true (fault reached WB retirement). The handling sequence: flush pipeline, enter PAL via m_pBox→enterPal() with the appropriate PalEntryReason and vector, drain write buffers if needed, issue memory barrier if needed.
handleRedirect(reason, metadata1, metadata2) provides a unified dispatch for all control flow changes. The RedirectReason enum classifies redirects:
None — no redirect. BranchMisprediction, BranchTaken, Jump, JumpSubroutine, Return, Coroutine — set PC to target, flush pipeline if misprediction. PALEntry — compute CALL_PAL entry vector, enter PAL. PALReturn — restore context via restoreContext(). Trap — compute trap vector, enter PAL. Interrupt — compute interrupt vector, enter PAL. MachineCheck — compute MCHK vector, enter PAL.
See Also: Chapter 7 - Exceptions, Faults, and Interrupts; cpuCoreLib/RedirectReason.h.