<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 12 – AlphaCPU Core > 12.6 Pipeline Integration

AlphaCPU owns the AlphaPipeline and drives it explicitly. The pipeline is initialized when executeLoop() calls injectOtherBoxes() to connect all execution boxes. Each cycle, AlphaCPU calls m_alphaPipeline→tick(fetchResult), which advances all six stages (WB→MEM→EX→IS→ID→IF in reverse order to prevent data hazards) and returns a BoxResult.

 

AlphaCPU's responsibilities toward the pipeline: advance pipeline stages (via tick()), handle stalls (pipeline self-manages via slot.stalled), handle flushes (m_alphaPipeline→flush() called from enterPalMode, executeREI, handleInterrupt, handleRedirect), coordinate serialization (CBox barrier flags in pipeline slots), and commit architectural state in WB (pipeline writes register payloads during stage_WB).

 

AlphaCPU does not execute instructions directly — it delegates execution to the pipeline and grains. The grain→execute() call happens inside AlphaPipeline::stage_EX(), not in AlphaCPU code.

 

See Also: Chapter 3 - Pipeline Architecture; Chapter 13 – AlphaPipeline Implementation.