<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 18 – Fault Dispatcher & Precise Exceptions > 18.10 Architectural Invariants (Normative)

The following invariants govern the fault dispatch subsystem. Violation of any invariant constitutes an emulator bug.

 

Precise Delivery: All exceptions are precise. When a fault is delivered, all prior instructions have completed, the faulting instruction is identified (EXC_ADDR), and no later instruction has modified architectural state. Faults detected in EX are not delivered until WB.

 

No Partial Effects: No faulting instruction may partially commit. A faulting store never reaches SafeMemory. A faulting load never writes a result register. The pending commit is discarded in WB before any commit logic runs.

 

Single Authority: FaultDispatcher is the sole authority for event queueing and delivery on its CPU. No other component may deliver exceptions or modify event state. One FaultDispatcher per CPU, accessed via globalFaultDispatcher(cpuId).

 

Classification Consistency: ExceptionFactory is the sole constructor for PendingEvent instances. ExceptionMapping_inl::mapClassToPalVector() is the single source of truth for ExceptionClass → PalVectorId mapping. No detection point constructs raw PendingEvent or resolves PAL vectors directly.

 

PAL Exclusivity: All exception handlers are PAL code. No exception handler exists outside PAL. All delivery paths converge on enterPalMode().

 

Priority Enforcement: When multiple events are pending, the highest-priority event is delivered first. Lower-priority events remain queued. Interrupts (lowest priority) are never delivered while a synchronous fault is pending.

 

Reservation Clearing: Exception delivery and PAL mode entry clear LL/SC reservations. No STx_C may succeed across an exception boundary.

 

Hot Path Efficiency: eventPending() is a single bitfield test (~1 cycle, no atomics). The FaultDispatcher is per-CPU with no cross-CPU synchronization on the hot path.

 

See Also: Chapter 11 - Architectural Invariants (complete invariant reference); 11.2 Execution and Pipeline Invariants (precise execution).