19.3 Interrupt Routing

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19.3 Interrupt Routing

19.3.1 InterruptRouter

 

InterruptRouter (coreLib/InterruptRouter.h, ~505 lines) handles interrupt routing policy — determining which CPU receives a given interrupt in SMP configurations. It provides per-vector routing configuration and supports four routing policies:

 

Policy

Behavior

FIXED_CPU

Affinity-pinned — interrupt always delivered to a specific CPU. Default policy, routes to CPU 0.

ROUND_ROBIN

Load distribution — interrupts rotate across CPUs for balanced handling.

LOWEST_IPL

Target the CPU currently at the lowest IPL — interrupt is most likely to be immediately deliverable.

BROADCAST

Deliver to all CPUs simultaneously — used for system-wide notifications.

 

The routing policy is configured per device in the IrqTemplate within DeviceTemplate (see Chapter 16). The default is FIXED_CPU targeting CPU 0, which matches typical Alpha system configurations. InterruptRouter also handles IPI dispatch — routing IPI messages from the source CPU to the target CPU's IRQPendingState.

 

 

19.3.2 Priority and Masking Rules

 

Interrupt delivery is gated by several conditions. An interrupt is deliverable only when: its IPL exceeds the current processor IPL (PS.IPL), interrupts are enabled in the processor state, the CPU is not in the middle of a serialized barrier, and the CPU is not in a PAL entry sequence (except for machine checks, which override PAL mode).

 

Higher IPL masks lower-priority interrupts. Machine checks override all masking. IPIs respect IPL. Software interrupts at IPL 1–15 follow the same masking rules as hardware interrupts. ASTs are gated at IPL 2 and additionally by the AST enable mask and current processor mode.

 

Masked interrupts remain pending in IRQPendingState until they become deliverable. They are not lost — the pending state persists until claimed or cleared.

 

See Also: coreLib/InterruptRouter.h (~505 lines); 16.10 Device Registration and Template System (IrqTemplate routing policy).