<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 19 – Interrupt Architecture & IPI > 19.4 Interrupt Sampling and Delivery

Interrupts are sampled during the pre-cycle phase of the AlphaCPU run loop, before pipeline advancement. The delivery sequence for the CPU thread each cycle:

 

AlphaCPU::checkInterrupts()

 │

 ├── 1. Read current IPL from PS

 │

 ├── 2. Test IRQPendingState::hasDeliverable(currentIPL)

 │ (single atomic load + compare, ~5 cycles)

 │ Nothing pending → return immediately

 │

 ├── 3. claimNext() → ClaimedInterrupt{source, IPL, vector}

 │ Atomically claim highest-priority interrupt

 │

 ├── 4. Clear SISR bit (if software interrupt)

 │

 ├── 5. Break LL/SC reservation

 │ ReservationManager::breakReservation(cpuId)

 │

 ├── 6. PalService::deliverInterrupt(claimed)

 │ Save PC and PS

 │ Select interrupt PAL vector

 │ enterPalMode(INTERRUPT, vector, currentPC)

 │

 └── 7. Flush pipeline

 

Interrupts are never injected mid-instruction. The check occurs at instruction boundaries, after the previous instruction has fully retired. When an interrupt is delivered, the pipeline is flushed and control transfers to the PAL interrupt handler. The handler identifies the interrupt source, services it, and returns via HW_REI.

 

Invariant: Synchronous faults always take priority over interrupts. If a fault is pending in the FaultDispatcher, interrupt delivery is blocked until the fault is resolved. The delivery order is: synchronous fault → machine check → deliverable interrupt → resume execution.

 

See Also: cpuCoreLib/AlphaCPU.h – checkInterrupts(); 18.6 Pipeline Fault Detection and Delivery Flow; palLib_EV6/Pal_Service.h – deliverInterrupt().