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This chapter describes the implementation of the EMulatR interrupt and inter-processor interrupt (IPI) subsystem: how interrupts are generated, routed, prioritized, masked, and delivered, and how IPIs coordinate SMP operations such as TLB shootdowns and memory barrier synchronization. Where Chapter 7 defines the architectural contract and Chapter 18 describes the FaultDispatcher that queues and delivers events, this chapter covers the concrete interrupt tracking structures, routing logic, IPI protocol, and cross-CPU coordination mechanisms.

 

The interrupt subsystem follows a core design principle: interrupts are architectural events, not pipeline side effects. All interrupts — whether from devices, software, or other CPUs — flow through the same prioritization, masking, and PAL delivery path. EMulatR intentionally does not create a second interrupt system for IPIs; they are injected into the same interrupt infrastructure and differ only in source, not delivery.

 

Scope: This chapter covers IRQPendingState (per-CPU interrupt tracking), InterruptRouter (routing policies), IPIManager (lock-free IPI delivery), IPICommand encoding, software interrupts (SIRR/SISR), AST delivery, MemoryBarrierCoordinator, TLB shootdown protocol, and SMP safety guarantees. It does not cover device interrupt assertion (Chapter 16), FaultDispatcher internals (Chapter 18), or PAL handler code (Chapter 20).

 

See Also: Chapter 7 - Exceptions, Faults, and Interrupts  (architectural contract); Chapter 18 – Fault Dispatcher & Precise Exceptions (event delivery); Chapter 16 – Device Model & DMA (device interrupt assertion).