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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 19 – Interrupt Architecture & IPI > 19.1 Interrupt Sources |
External devices (MMIO controllers, timers, disks, NICs) assert interrupts when DMA completes, an error occurs, or a status threshold is reached. Devices assert an IRQ line via IRQPendingState but never directly invoke CPU code or stall the pipeline. Device interrupt assertion is cross-thread: a device I/O thread (QThread) may raise an interrupt at any time while the CPU thread is executing instructions. This drives the atomic design of IRQPendingState.
Software interrupts are raised by CPU instructions or PAL code via the SIRR (Software Interrupt Request Register). Writing MTPR_SIRR sets a bit in the software interrupt request bitmap (bits [15:1] for IPL 1–15). The SISR (Software Interrupt Summary Register) is the read-only view of pending software interrupt state. Software interrupts use the same interrupt delivery path as hardware interrupts and obey the same IPL masking rules.
MTPR_SIRR updates IPR state only — it does not directly cause interrupt delivery. Pending software interrupts are evaluated at instruction retirement boundaries by the CPU run loop, and delivery is performed through PalService, identically to hardware interrupts.
ASTs are deferred interrupts that deliver signals or notifications to specific processor modes. The AST subsystem uses four IPR registers maintained in the HWPCB (Hardware Process Control Block):
Register |
Purpose |
|---|---|
ASTEN |
AST Enable — bitmask of which AST levels (0–3, one per mode) are enabled |
ASTER |
AST Enable Request — enable bits maintained by PAL/OS |
ASTRR |
AST Request — write by OS or PAL requesting an AST at a given level |
ASTSR |
AST Summary — hardware-computed: ASTSR = ASTRR & ASTEN, reflects pending-and-enabled ASTs |
AST delivery is gated by IPL (AST interrupts fire at IPL 2) and current mode. ASTs do not cross CPUs — the OS arranges delivery to a specific CPU. All four AST registers are part of process context and must be saved/restored on context switches. The checkPendingAST() method computes the effective ASTSR and determines if an AST is deliverable at the current IPL and mode.
IPIs are CPU-to-CPU notifications used for SMP coordination: TLB shootdowns, memory barrier synchronization, scheduler notifications, CPU halt/wake, and context switch requests. IPIs are generated by one CPU (via MTPR_IPIR or WRIPIR PAL instructions), routed via IPIManager, and delivered to the target CPU as interrupts through the same delivery path as device interrupts.
See Also: 7.10 Interrupt Handling; 16.8 IRQ Integration Architecture (device interrupt flow).