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This chapter describes the implementation of the EMulatR device subsystem: how devices are constructed, differentiated, routed through MMIO, threaded for asynchronous I/O, and integrated with DMA and interrupt delivery. Where Chapter 10 defines the architectural contract — MMIO is strongly ordered, devices are asynchronous, completion is interrupt-driven — this chapter describes the concrete classes, managers, threading model, storage backends, and bus topologies that deliver those guarantees.

 

Implementation Status: The device and DMA subsystem is a work in progress. The MMIO dispatch engine (MMIOManager), device registration catalog (DeviceCatalog, DeviceTemplate), DMA coherency manager (DMACoherencyManager), and IRQ integration infrastructure are structurally complete and represent approximately 1,800 lines of production header code. The IDeviceEmulator interface contract is stable. Individual device emulators — SCSI disk, SCSI tape, network adapters, Fibre Channel storage, IDE controllers — are at varying stages of implementation. The interfaces are designed for incremental plug-in: each device manager can be developed, tested, and attached independently without modifying the core MMIO or interrupt infrastructure.

 

Estimated Structural Readiness: The MMIO routing layer, device template system, and interrupt signaling path are ready for device integration. The DMA coherency path (TX flush, RX invalidation, LL/SC reservation breaking) is implemented but requires validation under multi-device SMP load. Individual device emulators should be considered scaffolded — the interface contracts exist, the managers are instantiable, but full behavioral fidelity to Alpha hardware device protocols is ongoing. The system is designed so that new devices can be plugged into the existing infrastructure via DeviceCatalog registration and MMIOManager region binding without changes to the pipeline, memory system, or interrupt delivery paths.

 

Scope: This chapter covers device differentiation, MMIO routing implementation, endianness handling, asynchronous I/O threading, storage backends (including tape format variants), DMA implementation, and the current IRQ integration architecture. It does not cover TLB or address translation (Chapter 17) or fault dispatch mechanics (Chapter 18).

 

See Also: Chapter 10 – Devices and Memory-Mapped I/O (MMIO) (architectural contract); Chapter 15 – Memory System Implementation Details (GuestMemory PA routing, MMIO access semantics); Chapter 14 – Execution Domains (“Boxes”)  (MBox, CBox device interaction).