<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 19 – Interrupt Architecture & IPI > 19.7 TLB Shootdown Protocol

TLB shootdown is the primary use case for IPIs. When a CPU modifies page tables, other CPUs may have stale TLB entries. Without invalidation, memory safety would be violated — stale entries could allow access to freed pages, bypass permission changes, or map incorrect physical addresses.

 

Shootdown Sequence:

 1. CPU A modifies page table entries in GuestMemory

 2. CPU A performs local TLB invalidation (TBIS/TBIA on own TLB)

 3. CPU A sends TLB invalidation IPIs to all other CPUs

 IPICommand selects scope:

 TLB_INVALIDATE_VA_ITB → single VA, ITB only

 TLB_INVALIDATE_VA_DTB → single VA, DTB only

 TLB_INVALIDATE_VA_BOTH → single VA, ITB + DTB

 TLB_INVALIDATE_ASN → all entries for ASN

 TLB_INVALIDATE_ALL → flush all TLB entries

 VA-specific: VA encoded via encodeIPIWithVA()

 ASN-specific: ASN encoded via encodeIPIWithASN()

 4. Target CPUs receive IPI via checkInterrupts()

 Enter PAL mode

 Call handleTLBShootdownIPI(cpuId, ipiData)

 Decode IPICommand, perform TLB invalidation on local ITB/DTB

 5. Target CPUs acknowledge completion

 6. CPU A resumes after all targets acknowledge

 

Shootdowns are serialized operations — the initiating CPU stalls until all targets have acknowledged. No global locks are required; the protocol uses per-CPU atomic IPI slots and acknowledgment counts.

 

Invariant: Shootdown is always explicit and synchronized. No CPU may execute with a stale TLB entry after a shootdown completes. Reservation clearing is a mandatory side effect of TLB invalidation (see Chapter 17).

 

See Also: 9.8 TLB Shootdown; 17.8 TLB Invalidation and Shootdown; cpuCoreLib/AlphaCPU.h – handleTLBShootdownIPI().