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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 19 – Interrupt Architecture & IPI > 19.6 Memory Barrier Coordination |
MemoryBarrierCoordinator (memoryLib/MemoryBarrierCoordinator.h, ~278 lines) is a singleton accessed via global_MemoryBarrierCoordinator() that manages global memory barrier synchronization across all CPUs. It tracks barrier state: barrierInProgress (atomic bool), initiatingCpu, participatingCpus count, waitingCpus count (atomic), acknowledgedCpus count (atomic), and a QWaitCondition (barrierComplete) for blocking the initiating CPU until all acknowledgments arrive.
When CPU N executes MB in an SMP configuration:
1. CBox::executeMB() drains the local write buffer
2. CBox::RequestMemoryBarrier()
→ ExecutionCoordinator::requestMemoryBarrier(cpuId)
3. MemoryBarrierCoordinator::initiateGlobalMemoryBarrier(cpuId, activeCpuCount)
If activeCpuCount == 1 → barrier completes immediately (returns false)
If barrier already in progress → CPU joins existing barrier (returns false)
4. Coordinator initializes barrier state
Initiating CPU self-acknowledges immediately
5. ExecutionCoordinator sends MEMORY_BARRIER_FULL IPIs to all other active CPUs
encodeIPIData(IPICommand::MEMORY_BARRIER_FULL, 0)
6. Initiating CPU calls waitForBarrierAcknowledge(cpuId)
Blocks on QWaitCondition with 2-second timeout
7. Target CPUs: receive IPI → enter PAL → drain write buffers
→ call acknowledgeMemoryBarrier(cpuId)
8. All CPUs acknowledged → QWaitCondition signaled
barrierInProgress cleared → initiating CPU resumes
WMB is local-only — it drains the local write buffer with no global coordination and no IPIs. This makes WMB significantly cheaper than MB in SMP configurations. MB requires global coordination when activeCpuCount > 1. PAL barriers (MemoryBarrierKind::PAL) use the same global coordination path as MB.
If the 2-second timeout expires before all CPUs acknowledge, the coordinator raises a machine check event (MachineCheckReason::SMP_BARRIER_TIMEOUT) via the FaultDispatcher. The MCES register's MME bit determines whether this is a fatal error or suppressed. This prevents a hung CPU from deadlocking the system — the timeout acts as a safety valve for SMP correctness.
See Also: memoryLib/MemoryBarrierCoordinator.h (~278 lines); emulatrLib/ExecutionCoordinator.h – requestMemoryBarrier(); 9.7 Memory Barrier Coordination; Chapter 6 - Serialization and Stall Model.