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The following invariants govern the interrupt and IPI subsystem. Violation of any invariant breaks SMP correctness.

 

Unified Interrupt Path: All interrupts — device, software, IPI — flow through IRQPendingState and the same PAL delivery mechanism. No interrupt source may bypass this path.

 

Interrupt Sampling: Interrupts are sampled at instruction boundaries, never mid-instruction. The sampling point is the pre-cycle phase of the CPU run loop, after barrier release checks.

 

Fault Priority: Synchronous faults always outrank interrupts. If a fault is pending in the FaultDispatcher, interrupt delivery is blocked until the fault is resolved.

 

PAL Serialization: All interrupt handlers are PAL code. Interrupt delivery serializes the pipeline and enters PAL mode. No interrupt handler exists outside PAL.

 

No Lost Interrupts: Level-triggered interrupts remain pending until claimed and serviced. Edge-triggered interrupts are recorded on assertion. The IRQPendingState atomic operations ensure no interrupt is lost due to race conditions between device threads and the CPU thread.

 

IPI Explicitness: IPIs are per-CPU and explicit. Every IPI has a defined source CPU, target CPU, and command. No implicit cross-CPU interrupt generation occurs.

 

Reservation Clearing: LL/SC reservations are cleared on every interrupt delivery and PAL mode entry. No STx_C may succeed across an interrupt boundary.

 

Barrier Ordering: Interrupt delivery does not bypass memory ordering. Barriers ensure all memory effects complete before interrupt handling. Interrupt handlers see consistent memory state.

 

Shootdown Synchrony: TLB shootdown via IPI is serialized — the initiating CPU stalls until all target CPUs have acknowledged. No CPU may execute with a stale TLB entry after shootdown completion.

 

Per-CPU Independence: Each CPU handles interrupts independently. There is no global interrupt lock. Cross-CPU coordination uses only atomic operations, IPIs, and the MemoryBarrierCoordinator.

 

See Also: Chapter 11 - Architectural Invariants (complete invariant reference).