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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 8 - PAL and Privileged Boundary > 8.6 PAL Execution Model |
PAL code executes using the same instruction set and the same pipeline as normal code. It uses general-purpose registers (with shadow registers active during PAL mode), floating-point registers (if enabled), and may access IPRs directly via HW_MFPR/HW_MTPR. There is no separate PAL pipeline.
In PAL mode, the following operations become legal:
•Privileged instructions: HW_MFPR (opcode 0x19), HW_MTPR (opcode 0x1D), HW_LD (opcode 0x1B), HW_ST (opcode 0x1F), HW_REI
•IPR access — read/write of all Internal Processor Registers
•Cache and TLB manipulation — TBI, TBIS, DTB/ITB invalidation
•Physical memory access — HW_LD/HW_ST bypass normal VA→PA translation
•Certain faults are masked or deferred during PAL execution
•Interrupt behavior is controlled explicitly (IPL = 7 on entry)
Outside PAL mode, all of these operations generate an OPCDEC (illegal instruction) fault.
See Also: 4.9 PalBox - Privileged Architecture Library Box (175 execute methods).