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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 8 - PAL and Privileged Boundary > 8.7 PAL and Exceptions/Interrupts |
All architecturally visible exceptions ultimately enter PAL. The delivery sequence: fault detected in EX → FaultDispatcher queues event → faulting instruction reaches WB → pipeline is flushed → state is saved via saveContext() → PAL vector is selected (from PalVectorId_EV6) → execution transfers to PAL handler via enterPal().
PAL is responsible for deciding whether to handle the exception internally, reflect it to the OS (via a second-level dispatch), or terminate execution.
On entry, EXC_ADDR contains the faulting PC, EXC_SUM contains the exception summary, and PS reflects the pre-exception state. PAL code consumes and interprets this state.
Interrupts are delivered through PAL in the same manner as faults. Interrupts are masked on entry (IPL raised to 7), PAL interrupt handlers run at elevated IPL, PAL acknowledges device sources, and PAL determines the return path.
Inter-processor interrupts enter PAL mode on the target CPU, are dispatched via PAL vectors (PalVectorId_EV6::IPI_INTERRUPT = 0x0600), and may trigger TLB shootdowns or synchronize barrier completion. PAL is the only safe place to coordinate SMP state because it provides the serialized, privileged context needed for cross-CPU operations.
See Also: Chapter 7 - Exceptions, Faults, and Interrupts (detection and deliver mechanics).