<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 8 - PAL and Privileged Boundary > 8.8 PAL and Memory Ordering

PAL code is implicitly serialized. Entry implies a full barrier (equivalent to MB + EXCB), exit implies a barrier. This ensures that exception handlers see stable memory, context switches are consistent, and device state is coherent.

 

Specifically, on PAL entry: write buffers are drained via CBox::issueMemoryBarrier(MemoryBarrierKind::PAL), the global barrier coordinator synchronizes with other CPUs (in SMP), and the CBox state transitions from SERIALIZING back to RUNNING only after all acknowledgments are received.

 

Certain PAL operations explicitly drain buffers (e.g., MB instruction within PAL code, DRAINA). Memory ordering is guaranteed across PAL boundaries — this is a stronger guarantee than any single barrier instruction provides to non-PAL code.

 

See Also: 6.11 CALL_PAL as a Serialization Point.