<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 10 – Devices and Memory-Mapped I/O (MMIO) > 10.1 Purpose of This Chapter

This chapter defines how EMulatR models devices and memory-mapped I/O (MMIO), and how device interactions integrate with the AlphaCPU pipeline, the memory system, interrupt delivery, serialization and ordering, and SMP execution.

 

Devices are asynchronous entities, but MMIO access is synchronous and strongly ordered. This distinction is fundamental to correctness.

 

See Also: Section 5.7 – MMIO Regions; Chapter 7 – Exceptions, Faults, and Interrupts (interrupt delivery); Chapter 9 – SMP Architecture (device visibility).