<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 10 – Devices and Memory-Mapped I/O (MMIO) > 10.2 Design Philosophy

EMulatR follows real Alpha hardware principles for device modeling:

 

•MMIO is memory-mapped but not memory-like — device registers are accessed via load/store instructions at physical addresses, but they have side effects, strong ordering, and no caching.

•MMIO accesses are strongly ordered — no reordering, no buffering, no speculation, no combining, no deferral.

•Device operations are asynchronous — after receiving a command via MMIO, the device performs work independently of the CPU.

•Completion is signaled via interrupts — the CPU never spins waiting for a device unless software explicitly polls.

•CPU execution never blocks on device work — MMIO writes trigger device operations; results arrive later via interrupts.

•PAL mediates privileged device control — device initialization, interrupt routing, and DMA enablement require PAL mode.

 

See Also: 5.7 MMIO Regions (strong ordering rules).