<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 22 – Testing, Validation, and Architectural Compliance > 22.7 Device and DMA Validation

Device validation focuses on the contract between devices and the architectural execution model.

 

MMIO ordering: MMIO reads and writes respect the memory ordering model. Stores to MMIO regions are visible in program order after barriers. Device state changes are visible to the CPU only through architecturally defined paths (MMIO reads, interrupt delivery).

 

DMA correctness: DMA transfers write to GuestMemory through SafeMemory, producing the same visibility semantics as CPU stores. DMA completion signals arrive through the interrupt system. DMA + barrier interactions are verified (CPU stores before MB are visible to DMA engines, DMA stores before completion interrupt are visible to CPU after interrupt delivery).

 

Interrupt signaling: Device interrupts assert through IRQPendingState and follow the standard delivery path. Interrupt masking by IPL is respected. Interrupt acknowledgment clears the pending state correctly. SMP DMA visibility (DMA completion on one CPU visible to another after barrier) is verified.

 

Devices must never: Stall the CPU pipeline (devices execute on separate threads), bypass memory ordering rules (all device memory access goes through SafeMemory), or inject interrupts outside the IRQPendingState path.

 

MMIO bugs are ordering bugs until proven otherwise — device validation always traces MMIO reads/writes with CPU ID and correlates with barrier events.

 

See Also: Chapter 16 – Device Model & DMA (device architecture under test); Chapter 15 – Memory System Implementation Details  (SafeMemory and write buffer behavior).