|
<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 10 – Devices and Memory-Mapped I/O (MMIO) > 10.8 Asynchronous Operations and DMA |
After receiving a command via MMIO write, the device begins work asynchronously. CPU execution continues immediately. The device may perform DMA. Completion is deferred until the device signals via interrupt. The CPU never spins waiting for a device unless software explicitly polls a status register.
DMA allows devices to read from and write to GuestMemory directly, bypassing CPU caches (architecturally). DMA is subject to address translation rules, access permissions, and cache coherency management.
DMACoherencyManager (mmio_DMACoherencyManager.h, 579 lines) manages coherency between devices and CPUs:
•TX path (RAMToDevice) — flush CPU caches before device reads from RAM, ensuring device sees latest CPU writes
•RX path (DeviceToRAM) — invalidate CPU caches after device writes to RAM, ensuring CPU sees device data
•LL/SC invalidation — invalidate reservations on DMA writes via ReservationManager::breakReservationsOnCacheLine()
•SMP coordination — coordinate multi-CPU cache operations for DMA regions
DMABufferDescriptor tracks allocated DMA buffers: physical address, size, owning device UID, address mask (for 32-bit vs 64-bit devices), and coherency flag.
DMA completion does not imply ordering unless enforced by barriers or interrupts.
See Also: mmioLib/mmio_DMACoherencyManager.h.