<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 10 – Devices and Memory-Mapped I/O (MMIO) > 10.7 Device Registers and Side Effects

Devices expose control and status registers via MMIO. Typical register types include command registers, status registers, data registers, interrupt control registers (IMR/ISR), and DMA descriptors.

 

MMIO register access may have side effects:

•Writing a command register may start an asynchronous operation

•Reading a status register may clear bits (clear-on-read ISR)

•Writing an interrupt control bit may acknowledge an interrupt

•Writing a doorbell register triggers DMA/command processing — the IDeviceEmulator contract specifies that the device should call mmioManager->drainPostedWrites(uid) before reading descriptors to ensure CPU writes are visible

 

These side effects occur during the MMIO access itself — they are synchronous from the CPU's perspective. However, the work triggered by the side effect (DMA transfer, command processing) is asynchronous.

 

The sideEffectOnRead and sideEffectOnWrite flags in MMIOWindow allow the memory system and debugger to identify registers with side effects, preventing accidental re-reads during debugging or speculative access.

 

See Also: mmioLib/IDeviceEmulator.h (onRead, onWrite contracts).