10.6 MMIO Access Semantics

<< Click to Display Table of Contents >>

Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 10 – Devices and Memory-Mapped I/O (MMIO) >

10.6 MMIO Access Semantics

10.6.1 Strong Ordering Rules

 

MMIO accesses are strongly ordered: no reordering, no buffering, no speculation, no combining, no deferral. Every MMIO read or write completes synchronously, is visible immediately, and observes program order. This prevents device protocol violations.

 

MMIO writes bypass the write buffer entirely — they are committed directly through GuestMemory → MMIOManager → device handler, not deferred via WriteBufferManager.

 

10.6.2 Pipeline Behavior

 

MMIO access occurs during the EX stage via MBox. The instruction executes synchronously, the pipeline may stall for the duration, the result is returned immediately, and no write buffer is used. MMIO instructions retire only after the access completes.

 


 

10.6.3 MMIOStatus Return Codes

 

Device handlers return MMIOStatus to indicate success or failure:

 

enum class MMIOStatus : quint8 {

 OK = 0x0, // Success

 ALIGNMENT_FAULT, // Unaligned access

 BUS_ERROR, // Fatal bus error (machine check)

 DEVICE_ERROR, // Device-level error

 INVALID_ADDRESS, // No device at address

 PERMISSION_DENIED, // Read-only/write-only violation

 READ_ONLY, // Write to read-only register

 SIZE_VIOLATION, // Wrong access size

 TIMEOUT, // Device did not respond

 UNIMPL, // Register not implemented

 WIDTH_FAULT, // Unsupported width

 WRITE_ONLY // Read from write-only register

};

 

Non-OK status codes are translated to appropriate faults (bus error, alignment fault, access violation) by the memory system and delivered through the normal exception path.

 


 

10.6.4 MMIOWindow Access Attributes

 

Each MMIO window carries fine-grained access attributes set during resource allocation:

 

allowedWidths — bitmask: 0x01=byte, 0x02=word, 0x04=long, 0x08=quad

stronglyOrdered — serialize all accesses in MMIOManager (true for all MMIO by default)

sideEffectOnRead — read has side effects (FIFO pop, clear-on-read ISR)

sideEffectOnWrite — write has side effects (doorbell, FIFO push, command start)

regEndian — register endianness (Little/Big)

cachePolicy — always Uncacheable for MMIO

 

See Also: coreLib/mmio_core.h (MMIOStatus, MMIOWindow).