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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 10 – Devices and Memory-Mapped I/O (MMIO) > 10.9 Interrupt Signaling |
Devices signal completion via interrupts. The process: device completes work, device asserts interrupt line (via IRQPendingState), CPU samples interrupt during pre-cycle phase (via AlphaCPU::checkInterrupts()), interrupt is delivered through PAL (via PalService::deliverInterrupt()).
Each device has an assigned IRQ vector (from IrqTemplate) and IPL (typically IPL 20 for devices). Trigger mode is configurable: edge-triggered (one-shot) or level-triggered (held until acknowledged). IRQPendingState handles both modes via its inServiceMask for level-triggered sources.
Interrupt acknowledgment typically occurs via MMIO: CPU reads or writes a device register (e.g., ISR clear-on-read, interrupt acknowledge register write), device clears the interrupt condition, and the interrupt line is deasserted. PAL code often performs this acknowledgment as part of the interrupt handler.
See Also: 7.10 Interrupt Handling; coreLib/IRQPendingState.h.