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10.10.1 Implicit Ordering

 

MMIO accesses are implicitly serialized relative to each other. No explicit barrier is required to ensure ordering between two MMIO accesses or visibility of an MMIO write to the device. However, ordering relative to normal memory operations may require barriers.

 

10.10.2 Required Barrier Patterns

 

Common patterns that mirror real Alpha programming requirements:

 

MB before MMIO write — ensures prior memory writes (e.g., DMA descriptor setup in RAM) are visible before the device sees the command via MMIO.

 

MB after MMIO read — ensures device results (e.g., status register) are visible to the CPU before proceeding with dependent operations.

 

The IDeviceEmulator::onFence() callback allows devices to respond to barrier instructions — a device may need to drain internal posted write buffers or complete pending DMA when the CPU executes MB.

 

See Also: Chapter 6 - Serialization and Stall Model.