<< Click to Display Table of Contents >> Navigation:  ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 10 – Devices and Memory-Mapped I/O (MMIO) > 10.11 PAL and Device Control

Some device operations require PAL mode: device initialization, interrupt routing configuration, DMA enablement, and system-wide device control. Accessing these privileged registers outside PAL faults with OPCDEC.

 

All device interrupts ultimately enter PAL. PAL code identifies the interrupt source, acknowledges the device (typically via MMIO register write), invokes the OS handler, and returns via HW_REI. This ensures controlled, serialized device interaction.

 

See Also: Chapter 8 - PAL and Privileged Boundary.