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<< Click to Display Table of Contents >> Navigation: ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 10 – Devices and Memory-Mapped I/O (MMIO) > 10.12 SMP and Error Handling |
In SMP systems: devices are globally visible (all CPUs can access any MMIO region), MMIO ordering is global (strongly ordered regardless of which CPU initiates the access), interrupts may target specific CPUs (via IRQ affinity in IrqTemplate), DMA affects shared GuestMemory (visible to all CPUs after cache coherency operations), and barriers may be required for cross-CPU coordination when one CPU sets up DMA descriptors and another CPU initiates the device command.
Devices themselves are not CPU-affine unless explicitly configured. The IDeviceEmulator threading model specifies that onRead/onWrite may be called concurrently from multiple vCPU threads — devices must provide their own internal locking if needed.
MMIO access may generate faults: alignment faults (MMIOStatus::ALIGNMENT_FAULT), bus errors (MMIOStatus::BUS_ERROR → machine check), invalid address (MMIOStatus::INVALID_ADDRESS), permission violations (READ_ONLY, WRITE_ONLY, PERMISSION_DENIED), and device-specific errors (DEVICE_ERROR, TIMEOUT).
These faults are detected synchronously during the MMIO access, delivered precisely through the normal exception path, and enter PAL through exception vectors. Device errors do not corrupt CPU state.
Degraded devices are tracked via DegradedDeviceEntry and DegradedDeviceInfo structures — devices that fail initialization or resource allocation are recorded with the failure reason and timestamp, allowing the system to boot with reduced functionality rather than aborting.
See Also: Chapter 9 - SMP Architecture; coreLib/mmio_core.h (MMIOStatus, DegradedDeviceEntry).