ASA-EMulatR Reference Guide > Introduction > Architecture Overview > Chapter 10 – Devices and Memory-Mapped I/O (MMIO)

The EMulatR device and MMIO subsystem provides a strongly ordered, interrupt-driven device model that matches Alpha AXP hardware behavior.

MMIOManager — MMIO dispatch engine, region table, handler routing (114 lines)

IDeviceEmulator — abstract device interface, lifecycle and MMIO contract (266 lines)

mmio_core — MMIOStatus enum (15 values), mmio_DeviceClass enum (15 classes), MMIOWindow struct, allocation/degradation types (405 lines)

mmio_structs — supporting MMIO data structures (82 lines)

DeviceCatalog — template database, PCI ID lookup, class defaults (130 lines)

DeviceTemplate — complete device specification with PCI identity, BAR/IRQ requirements, DMA capabilities (208 lines)

DMACoherencyManager — DMA cache coherency, LL/SC invalidation, SMP coordination (579 lines)

Total: 1,784 lines across seven MMIO/device headers.

1.MMIO is strongly ordered — no reordering, no buffering, no speculation, writes bypass write buffer

2.Devices are asynchronous — MMIO commands trigger work; completion signals via interrupts

3.MMIO access is synchronous — completes in EX stage, pipeline may stall, result returned immediately

4.IDeviceEmulator defines the device contract — initialize, onRead, onWrite, onReset, onFence

5.MMIOManager routes by physical address — function-pointer handlers for maximum performance

6.DeviceCatalog provides template-based device registration — PCI ID, class, and custom key lookups

7.DMA operates on GuestMemory — DMACoherencyManager handles cache coherency and LL/SC invalidation

8.PAL mediates privileged device control — all device interrupts enter PAL

9.SMP devices are globally visible — concurrent vCPU access, device provides internal locking

10.Degraded devices are tracked, not fatal — system boots with reduced functionality

10.13 Summary